Gagliardi, Mirko
(2018)
A RECONFIGURABLE AND EXTENSIBLE EXPLORATION PLATFORM FOR FUTURE HETEROGENEOUS SYSTEMS.
[Tesi di dottorato]
| Item Type: |
Tesi di dottorato
|
| Lingua: |
English |
| Title: |
A RECONFIGURABLE AND EXTENSIBLE EXPLORATION PLATFORM FOR FUTURE HETEROGENEOUS SYSTEMS |
| Creators: |
| Creators | Email |
|---|
| Gagliardi, Mirko | mirko.gagliardi@gmail.com |
|
| Date: |
10 December 2018 |
| Number of Pages: |
121 |
| Institution: |
Università degli Studi di Napoli Federico II |
| Department: |
Ingegneria Elettrica e delle Tecnologie dell'Informazione |
| Dottorato: |
Ingegneria informatica ed automatica |
| Ciclo di dottorato: |
31 |
| Coordinatore del Corso di dottorato: |
| nome | email |
|---|
| Riccio, Daniele | daniele.riccio@unina.it |
|
| Tutor: |
| nome | email |
|---|
| Cilardo, Alessandro | UNSPECIFIED |
|
| Date: |
10 December 2018 |
| Number of Pages: |
121 |
| Uncontrolled Keywords: |
High-Performance Computing (HPC), FPGA, Heterogeneous computing, many-core, network-on-chips, direcoty-based coherence |
| Settori scientifico-disciplinari del MIUR: |
Area 09 - Ingegneria industriale e dell'informazione > ING-INF/05 - Sistemi di elaborazione delle informazioni |
[error in script]
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| Date Deposited: |
22 Jan 2019 22:17 |
| Last Modified: |
23 Jun 2020 14:15 |
| URI: |
http://www.fedoa.unina.it/id/eprint/12562 |
Abstract
Accelerator-based -or heterogeneous- computing has become increasingly
important in a variety of scenarios, ranging from High-Performance Computing (HPC) to embedded systems. While most solutions use sometimes
custom-made components, most of today’s systems rely on commodity highend CPUs and/or GPU devices, which deliver adequate performance while
ensuring programmability, productivity, and application portability. Unfortunately, pure general-purpose hardware is affected by inherently limited
power-efficiency, that is, low GFLOPS-per-Watt, now considered as a primary metric. The many-core model and architectural customization can
play here a key role, as they enable unprecedented levels of power-efficiency
compared to CPUs/GPUs. However, such paradigms are still immature and
deeper exploration is indispensable.
This dissertation investigates customizability and proposes novel solutions
for heterogeneous architectures, focusing on mechanisms related to coherence and network-on-chip (NoC). First, the work presents a non-coherent
scratchpad memory with a configurable bank remapping system to reduce
bank conflicts. The experimental results show the benefits of both using a
customizable hardware bank remapping function and non-coherent memories for some types of algorithms. Next, we demonstrate how a distributed
synchronization master better suits many-cores than standard centralized
solutions. This solution, inspired by the directory-based coherence mechanism, supports concurrent synchronizations without relying on memory
transactions. The results collected for different NoC sizes provided indications about the area overheads incurred by our solution and demonstrated
the benefits of using a dedicated hardware synchronization support. Finally, this dissertation proposes an advanced coherence subsystem, based
on the sparse directory approach, with a selective coherence maintenance
system which allows coherence to be deactivated for blocks that do not require it. Experimental results show that the use of a hybrid coherent and
non-coherent architectural mechanism along with an extended coherence
protocol can enhance performance.
The above results were all collected by means of a modular and customizable heterogeneous many-core system developed to support the exploration
of power-efficient high-performance computing architectures. The system is
based on a NoC and a customizable GPU-like accelerator core, as well as
a reconfigurable coherence subsystem, ensuring application-specific configuration capabilities. All the explored solutions were evaluated on this real heterogeneous system, which comes along with the above methodological
results as part of the contribution in this dissertation. In fact, as a key
benefit, the experimental platform enables users to integrate novel hardware/software solutions on a full-system scale, whereas existing platforms
do not always support a comprehensive heterogeneous architecture exploration.
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