Garofalo, Valeria
(2009)
Truncated Binary Multipliers with minimum Mean Square Error: analytical characterization, circuit implementation and applications.
[Tesi di dottorato]
(Inedito)
Tipologia del documento: 
Tesi di dottorato

Lingua: 
English 
Titolo: 
Truncated Binary Multipliers with minimum Mean Square Error: analytical characterization, circuit implementation and applications 
Autori: 
Autore  Email 

Garofalo, Valeria  valeria.garofalo@unina.it 

Data: 
30 Novembre 2009 
Numero di pagine: 
190 
Istituzione: 
Università degli Studi di Napoli Federico II 
Dipartimento: 
Ingegneria biomedica, elettronica e delle comunicazioni 
Scuola di dottorato: 
Ingegneria dell'informazione 
Dottorato: 
Ingegneria elettronica e delle telecomunicazioni 
Ciclo di dottorato: 
22 
Coordinatore del Corso di dottorato: 
nome  email 

Rinaldi, Niccolò  nirinald@unina.it 

Tutor: 
nome  email 

Napoli, Ettore  etnapoli@unina.it 

Data: 
30 Novembre 2009 
Numero di pagine: 
190 
Parole chiave: 
Truncated multiplier, truncated squarer, error analysis, minimum mean square error, maximum absolute error, FIR filter, temperature control 
Settori scientificodisciplinari del MIUR: 
Area 09  Ingegneria industriale e dell'informazione > INGINF/01  Elettronica 
Depositato il: 
24 Mag 2010 09:58 
Ultima modifica: 
30 Apr 2014 19:39 
URI: 
http://www.fedoa.unina.it/id/eprint/3904 
DOI: 
10.6092/UNINA/FEDOA/3904 
Abstract
In the wireless multimedia word, DSP systems are ubiquitous. DSP algorithms are computationally intensive and test the limits of battery life in portable device such as cell phones, hearing aids, MP3 players, digital video recorders and so on. Multiplication and squaring are the main operation in many signal processing algorithms (filtering, convolution, FFT, DCT, euclidean distance etc.), hence efficient parallel multipliers are desirable. A fullwidth digital nxn bits multiplier computes the 2n bits output as a weighted sum of partial products. A multiplier with the output represented on n bits output is useful, as example, in DSP datapaths which saves the output in the same n bits registers of the input. Note that the truncated multipliers are useful not only for DSP but also for digital, computational intensive, ASICs where the bitwidths at the output of the arithmetic blocks are chosen on the basis of systemrelated accuracy issues. Hence 2n bits of precision at the multiplier output are very often more than required. A truncated multiplier is an nxn multiplier with n bits output. Since in a truncated multiplier the n lesssignificant bits of the fullwidth product are discarded, some of the partial products are removed and replaced by a suitable compensation function, to tradeoff accuracy with hardware cost. Several techniques have been proposed in the Literature following this basic idea. The difference between the various circuits is in the choice and the implementation of the compensation circuit. The correction techniques proposed in the Literature are obtained through exhaustive search. This means that the results are only available for small n values and that the proposed approach are not extendable to greater bit widths. Furthermore the analytical characterization of the error is not possible. In this dissertation an innovative solution for the design and characterization of truncated multipliers is presented. The proposed circuits are based on the analytical calculation of the error of the truncated multiplier. This approach allows to have the description of a multiplier characterized by a minimum mean square error which gives a fast and low power VLSI implementation. Furthermore the analytical approach yields to a closed form expression of the mean square error and maximum absolute error for the proposed truncated multipliers. In this way the a priori knowledge of the output error is available. The errors are known for every bit width of the multiplier and it is also possible to decide, for a given bit width, which correction circuit has to be used in order to obtain a certain error. This analytical relation between the error and the parameters of hardware implementation is extremely important for the digital designer, since now it is possible to select the suitable implementation as a function of the desired accuracy. Proposed truncated multipliers overcome the previously proposed truncated multipliers since provide lower error, lower power dissipation, lower area occupation and also provide higher working frequency. The circuits are also easily implemented and allow an automatic HDL description as a function of bit width and desired error. The complete description of the errors for the truncated multipliers allows the use of these circuits as building blocks for more complex systems. It will be shown how the proposed multiplier can be used to design low area occupation FIR filters and an efficient PI temperature controller.
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