Cicalese, Roberta (2009) High-Resolution Time-to-Digital Converter in a Field Programmable Gate Array. [Tesi di dottorato] (Unpublished)

[img] PDF
Visibile a [TBR] Repository staff only

Download (5MB)
[error in script] [error in script]
Item Type: Tesi di dottorato
Lingua: English
Title: High-Resolution Time-to-Digital Converter in a Field Programmable Gate Array
Date: 28 November 2009
Number of Pages: 96
Institution: Università degli Studi di Napoli Federico II
Department: Scienze fisiche
Dottorato: Fisica fondamentale ed applicata
Ciclo di dottorato: 21
Coordinatore del Corso di dottorato:
Date: 28 November 2009
Number of Pages: 96
Uncontrolled Keywords: TDC; FPGA;
Settori scientifico-disciplinari del MIUR: Area 02 - Scienze fisiche > FIS/01 - Fisica sperimentale
Date Deposited: 07 Jun 2010 09:09
Last Modified: 02 Dec 2014 10:48


Timing in nuclear and particle physics refers to the measurement of very small time intervals. Examples of its use include measurement of lifetimes of excited nuclear states or elementary particles, time-of-flight, etc. In this list also, the determination of coincidences, which is essentially the determination of a zero time interval, should be included. The intervals, therefore, range from as little as a few pico-seconds to as large as a few microseconds. An instrument used for measuring a time interval is called “Time-to-Digital Converter” (TDC). To develop measurement system with characteristics including both reconfiguration and multi-functions, in general, a SRAM-based Field Programmable Gate Arrays (FPGA) is preferred. FPGA allow programming of highly complex circuitries by combining a large number of small simple elements and it is more suitable for the application system design with the requirements of fast time-to-market and low development cost. The general architecture of the TDC developed in this work is based on the classic Nutt method. A counter provides a large linear dynamic range and interpolation enables high resolution. The developed two-stage interpolation method provides a high interpolation ratio and makes it possible to reach a high resolution with a relatively low reference clock frequency. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Two synchronization schemes were developed: the first synchronisation circuit is for controlling the operation of the coarse counter, the second one generates the difference signal for the fine interpolation. The fine interpolation is realized using the Vernier delay line architecture. It consists of two tapped rows working in differential mode. The first is created as a chain of the latch flip-flops and the other as a chain of non-inverting buffers. The time to be measured is defined between the rising edges of the pulses START and STOP. During the time-to-digital conversion process, the STOP pulse follows the START pulse along the line, and all latches from the first cell up to the cell where the START pulse overtakes the STOP pulse are consecutively set. The tests executed on this TDC show that the architecture allows us to reach good time resolution of about 50 ps.


Downloads per month over past year

Actions (login required)

View Item View Item