Giordano, Raffaele (2010) A VLSI System-on-Chip for Particle Detectors. [Tesi di dottorato] (Inedito)

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Tipologia del documento: Tesi di dottorato
Lingua: English
Titolo: A VLSI System-on-Chip for Particle Detectors
Autori:
AutoreEmail
Giordano, Raffaelergiordano@na.infn.it
Data: 30 Novembre 2010
Numero di pagine: 130
Istituzione: Università degli Studi di Napoli Federico II
Dipartimento: Scienze fisiche
Scuola di dottorato: Scienze fisiche
Dottorato: Fisica fondamentale ed applicata
Ciclo di dottorato: 23
Coordinatore del Corso di dottorato:
nomeemail
Marrucci, Lorenzolorenzo.marrucci@na.infn.it
Tutor:
nomeemail
Aloisio, Albertoaloisio@na.infn.it
Data: 30 Novembre 2010
Numero di pagine: 130
Parole chiave: VLSI; FPGA; SoC; detectors; HEP
Settori scientifico-disciplinari del MIUR: Area 02 - Scienze fisiche > FIS/04 - Fisica nucleare e subnucleare
Area 02 - Scienze fisiche > FIS/01 - Fisica sperimentale
Depositato il: 08 Dic 2010 15:33
Ultima modifica: 30 Apr 2014 19:45
URI: http://www.fedoa.unina.it/id/eprint/8240
DOI: 10.6092/UNINA/FEDOA/8240

Abstract

In this thesis I present a System-on-Chip (SoC) I designed to offer a self-contained, compact data acquisition platform for micromegas detector monitoring. I carried on my work within the RD-51 collaboration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electrode, process the data and perform monitoring tests. The SoC is built around on a custom 8-bit microprocessor with internal memory resources and embeds the peripherals to be interfaced with the external ADC. Peripherals implement in hardware threshold checking, pedestal suppression, waveform recording and histogram building. The CPU has some attractive features for real-time applications: high working frequency, constant instruction execution time, short and fixed interrupt latency and a tiny logic footprint. The processor makes it possible to execute in software additional off-line data processing, such as averaging, FWHM calculation and peak finding. It includes an 8-bit IO bus for interfacing with external logic and a UART for RS232 communications. The architecture is fully portable to any technology for the implementation of digital circuits (e.g. VLSI CMOS or FPGAs). In fact, I implemented and tested a prototype in a Virtex-II Xilinx FPGA and I completed the layout of a standard-cell CMOS 90nm version of system. The performance in terms of clock frequency and logic resource occupation are discussed in the view of the deployment of the system with the detector and of the development of a multi-channel version of the system.

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