Russo, Salvatore (2010) Measurement and Simulation of Electrothermal Effects in Solid-State Devices for RF Applications. [Tesi di dottorato] (Unpublished)
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|Item Type:||Tesi di dottorato|
|Uncontrolled Keywords:||Electrothermal effects, bipolar transistors, thermal effects, thermal resistance, thermal impedance, silicon-on-glass, thermal networks, self-heating, safe operating area|
|Date Deposited:||13 Dec 2010 10:40|
|Last Modified:||30 Apr 2014 19:45|
The past decades have seen an unmatched advancement of semiconductor industry. The constant need to improve the performances of solid-state devices has driven the research toward the study and fabrication of faster devices/circuits. Nevertheless, the demand for reduced parasitics necessary to guarantee improved (with respect to previous generation devices) performances has forced researchers to adopt increasingly aggressive isolation schemes (i.e., silicon-on-glass technology). The major drawback of aggressive isolation schemes is connected to the fact that most of the good electrical insulators are also characterized by a low thermal conductivity that can deteriorate the thermal path and may impose a limit on the current density for high speed devices. Thermal problems can also arise because of the particular semiconductor material used. During the past years there was a rapid ascent in the use of innovative materials like III-V compound semiconductors (like GaAs, InP, GaN etc...). These materials have been introduced to replace silicon because of the better performances from an electrical point of view. However, they often present worse thermal properties; GaAs, for example, has a thermal conductivity equal to a third of that of silicon. Moreover, the continuous request of integrating even more features in a single chip and the consequent miniaturization of the single device (an aggressive scaling) contribute to the power density increase. Nowadays, the power density of a commercial processor is comparable to the one of a nuclear reactor. Modern - even low-power - electronic devices/circuit can suffer from electrothermal effects at the point that these can hamper the reliability and performances. In this thesis, an approach to the analysis of solid-state devices ranging from simulations to measurements has been proposed with the aim to optimize thermal behavior at device level. For this purpose an advanced software has been conceived to automatically run detailed 3-D FEM simulations using layout and technology data. This software can be extensively used to deepen the comprehension of thermal issues in solid-state devices and to understand the influence of the main technology and layout parameters on devices/circuits electrothermal behavior. In particular, is has been successfully applied to analyze a large variety of technologies, namely, SOG BJTs, GaAs HBTs, GaN HEMTs, SiGe HBTs, and UTCS technology devices, thus favoring the definition of useful guide-lines to improve their thermal management. Moreover,an effective equivalent network identification tool has been developed to extract network data from thermal transients with modeling and analysis purposes. A novel compact thermal model has been proposed in order to reduce the simulation complexity still maintaining a good level of accuracy has been successfully demonstrated. Furthermore, a novel thermal resistance DC measurement technique has been proposed, which enables and accurate evaluation of thermal resistance of bipolar junction transistors regardless of the presence of Early effect. An electrothermal tool has been developed, which is based on the improvement of commercial circuit simulators. All the relevant physical effects, as well as self-heating and thermal coupling mechanisms are included, so as to guarantee an accurate prediction of the safe operating area borders of the analyzed devices. As a result, the tool can be successfully employed to support the design stage so as to improve the thermal ruggedness of the transistors of interest.
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