Gallo, Luca (2015) Methodologies for automated synthesis of memory and interconnect subsystems in parallel architectures. [Tesi di dottorato]

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Item Type: Tesi di dottorato
Lingua: English
Title: Methodologies for automated synthesis of memory and interconnect subsystems in parallel architectures
Creators:
CreatorsEmail
Gallo, Lucaluca.gallo@unina.it
Date: 29 March 2015
Number of Pages: 171
Institution: Università degli Studi di Napoli Federico II
Department: Ingegneria Elettrica e delle Tecnologie dell'Informazione
Scuola di dottorato: Ingegneria dell'informazione
Dottorato: Ingegneria informatica ed automatica
Ciclo di dottorato: 27
Coordinatore del Corso di dottorato:
nomeemail
Garofalo, Francescofrancesco.garofalo@unina.it
Tutor:
nomeemail
Cilardo, AlessandroUNSPECIFIED
Date: 29 March 2015
Number of Pages: 171
Uncontrolled Keywords: parallel architectures; hardware synthesis; on-chip interconnections
Settori scientifico-disciplinari del MIUR: Area 09 - Ingegneria industriale e dell'informazione > ING-INF/05 - Sistemi di elaborazione delle informazioni
Aree tematiche (7° programma Quadro): TECNOLOGIE DELL'INFORMAZIONE E DELLA COMUNICAZIONE > Macchine "più intelligenti", servizi migliori
Date Deposited: 23 Apr 2015 15:57
Last Modified: 30 Sep 2015 16:41
URI: http://www.fedoa.unina.it/id/eprint/10072
DOI: 10.6092/UNINA/FEDOA/10072

Abstract

As frequency scaling for single-core computers has today reached practical limits, the only effective source for improving computing performance is parallelism. Consequently, automated design approaches leveraging on parallel programming paradigms, such as OpenMP, appear a viable strategy for designing on-chip systems. At the same time, emerging architectures, such as reconfigurable hardware platforms, can provide unparalleled performance and scalability; in fact they allow to customize memory and communication subsystems based on the application needs. However, current high level synthesis tools often lack enough intelligence to capture those opportunities consequently leaving room for research. As a first contribution of this thesis, a novel technique based on integer lattices is proposed for tailoring the memory architecture to the application accesses pattern. Data are automatically partitioned across the available memory banks reducing conflicts so as to improve performance. Compared to existing techniques, the rigorous spatial regularity of lattices yields more compact circuits. As a second aspect, in order to sustain the execution parallelism stemming from the presence of multiple memory banks, an efficient interconnection subsystem must be designed. To this aim, the thesis proposes a methodology capable of targeting the interconnect to the traffic profile imposed by the distributed memory. In conclusion, all the proposed techniques are merged together in a comprehensive OpenMP-based design flow, resulting in an automated framework that well fits in the electronic design automation panorama.

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