Capasso, Luciano
(2010)
The monitoring system of the ATLAS muon spectrometer read out driver.
[Tesi di dottorato]
(Inedito)
| Tipologia del documento: |
Tesi di dottorato
|
| Lingua: |
English |
| Titolo: |
The monitoring system of the ATLAS muon spectrometer read out driver |
| Autori: |
| Autore | Email |
|---|
| Capasso, Luciano | spiderlux@gmail.com |
|
| Data: |
29 Novembre 2010 |
| Numero di pagine: |
131 |
| Istituzione: |
Università degli Studi di Napoli Federico II |
| Dipartimento: |
Scienze fisiche |
| Scuola di dottorato: |
Scienze fisiche |
| Dottorato: |
Fisica fondamentale ed applicata |
| Ciclo di dottorato: |
23 |
| Coordinatore del Corso di dottorato: |
| nome | email |
|---|
| Marrucci, Lorenzo | marrucci@na.infn.it |
|
| Tutor: |
| nome | email |
|---|
| Aloisio, Alberto | aloisio@na.infn.it |
|
| Data: |
29 Novembre 2010 |
| Numero di pagine: |
131 |
| Parole chiave: |
ROD read out driver ATLAS muon spectrometer monitoring microprocessor microblaze real time |
| Settori scientifico-disciplinari del MIUR: |
Area 02 - Scienze fisiche > FIS/04 - Fisica nucleare e subnucleare
Area 02 - Scienze fisiche > FIS/01 - Fisica sperimentale |
[error in script]
[error in script]
| Depositato il: |
08 Dic 2010 15:20 |
| Ultima modifica: |
30 Apr 2014 19:44 |
| URI: |
http://www.fedoa.unina.it/id/eprint/8151 |
| DOI: |
10.6092/UNINA/FEDOA/8151 |
Abstract
My PhD work focuses upon the Read Out Driver (ROD) of the ATLAS Muon Spectrometer. The ROD is a VME64x board, designed around two Xilinx Virtex-II FPGAs and an ARM7 microcontroller and it is located off-detector, in a counting room of the ATLAS cavern at the CERN. The readout data of the ATLAS’ RPC Muon spectrometer are collected by the front-end electronics and transferred via optical fibres to the ROD boards in the counting room. The ROD arranges all the data fragments of a sector of the spectrometer in a unique event. This is made by the Event Builder Logic, a cluster of Finite State Machines that parses the fragments, checks their syntax and builds an event containing all the sector data. In the presentation I will describe the Builder Monitor, developed by me in order to analyze the Event Builder timing performance. It is designed around a 32-bit soft-core microprocessor, embedded in the same FPGA hosting the Builder logic. This approach makes it possible to track the algorithm execution in the field. The Monitor performs real time and statistical analysis of the state machine dynamics. The microprocessor is interfaced with custom peripherals which read out the state registers, fill histograms and transfer them via DMA to the processor memory. The Builder Monitor also measures the elapsed time for each event, its length and keeps track of the error status words.
In my thesis I will describe the hardware-software co-design of the Builder Monitor and the role played by the custom peripherals. I will also present experimental results and the procedure I developed to check out errors and to debug software.
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