Tessitore, Fabio (2014) Agile All-digital Clock Generators with Spread-Spectrum Capabilities in 28nm technology. [Tesi di dottorato]


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Item Type: Tesi di dottorato
Lingua: English
Title: Agile All-digital Clock Generators with Spread-Spectrum Capabilities in 28nm technology
Tessitore, Fabiofabio.tessitore@unina.it
Date: 31 March 2014
Number of Pages: 97
Institution: Università degli Studi di Napoli Federico II
Department: Ingegneria Elettrica e delle Tecnologie dell'Informazione
Scuola di dottorato: Ingegneria dell'informazione
Dottorato: Ingegneria elettronica e delle telecomunicazioni
Ciclo di dottorato: 26
Coordinatore del Corso di dottorato:
Rinaldi, Niccolònirinald@unina.it
Date: 31 March 2014
Number of Pages: 97
Uncontrolled Keywords: Clock synthesis, delay interpolator, digitally controlled delay line, digitally controlled oscillator (DCO), EMI reduction, injection locking, spread-spectrum clock generator (SSCG).
Settori scientifico-disciplinari del MIUR: Area 09 - Ingegneria industriale e dell'informazione > ING-INF/01 - Elettronica
Date Deposited: 08 Apr 2014 11:32
Last Modified: 26 Jan 2015 11:56
URI: http://www.fedoa.unina.it/id/eprint/9739


The spread spectrum clocking (SSC) is an established, effective and efficient technique to reduce the electromagnetic interference (EMI) produced by digital chips. This method allows to reduce the level of EMI of digital circuit by intentionally sweeping the frequency of the clock signal (frequency modulated) within a certain frequency range in order to evenly spread the energy of each clock harmonic over a given bandwidth, reducing in this way the peak power level of radiated EMI. In this thesis, a novel All-digital Spread Spectrum Clock Generator (SSCG) prototype is presented in all its aspects: design, simulation and post-fabrication measurements. The circuit is realized by using a design flow completely based on standard cells simplifying design and porting in new technologies, and is able to perform both discontinuous frequency modulation or complex modulation profiles. The circuit uses four digitally controlled delay lines and two digital delay interpolator driven by a digital modulator to synthesize the output waveform A chip has been implemented in a 28nm CMOS technology. The chip is able to generate signals up to 3.3GHz. The measured peak level reduction of the clock spectrum, at 1GHz output frequency, is 27dB with a 10% modulation depth. The power dissipation is 24mW. In the second part of this thesis the first developed SSCG has been redesigned in order to allow the generation of an output clock signal with a frequency higher than the frequency of the input clock signal. To this purpose a new delay line block has been designed in order to implement the clock frequency multiplication. Furthermore, the injection locking technique is implemented by using a novel DCO-based architecture in order to improve the jitter performance of the circuit. The circuit is designed by using only standard cells and is able to generate an output clock frequency larger of 2GHz.


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