Genovese, Mariangela (2014) Hardware architectures for real time processing of High Definition video sequences. [Tesi di dottorato]


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Item Type: Tesi di dottorato
Lingua: English
Title: Hardware architectures for real time processing of High Definition video sequences
Date: 28 March 2014
Number of Pages: 123
Institution: Università degli Studi di Napoli Federico II
Department: Ingegneria Elettrica e delle Tecnologie dell'Informazione
Scuola di dottorato: Ingegneria dell'informazione
Dottorato: Ingegneria elettronica e delle telecomunicazioni
Ciclo di dottorato: 26
Coordinatore del Corso di dottorato:
Rinaldi, Niccolò
Date: 28 March 2014
Number of Pages: 123
Uncontrolled Keywords: Real time processing; High Definition video; Field Programmable Gate Array; Background identification; Denoising
Settori scientifico-disciplinari del MIUR: Area 09 - Ingegneria industriale e dell'informazione > ING-INF/01 - Elettronica
Date Deposited: 08 Apr 2014 11:31
Last Modified: 31 Dec 2017 02:00
DOI: 10.6093/UNINA/FEDOA/9727


Actually, application fields, such as medicine, space exploration, surveillance, authentication, HDTV, and automated industry inspection, require capturing, storing and processing continuous streams of video data. Consequently, different process techniques (video enhancement, segmentation, object detection, or video compression, as examples) are involved in these applications. Such techniques often require a significant number of operations depending on the algorithm complexity and the video resolution, which make impossible a time efficient software implementation. The actual demand, driven by the consumer electronics market, of lightweight and high performance portable systems capable of processing high definition (HD) video sequences in real-time is therefore mainly targeted through the use of integrated digital electronic systems. Very high performance can be obtained by using full custom ASIC implementations. However, the complexity and the cost associated with ASIC design is significant. Moreover, ASIC implementations are not reconfigurable and require a long design time. For these reasons, Field Programmable Gate Array (FPGA) devices are more and more being chosen as target technology for the hardware acceleration. In this dissertation, several hardware architectures for real-time video processing of HD video sequences are proposed. The circuits are designed by using Hardware Description Languages (HDL) and the target technologies for the implementation are mainly FPGA devices. Area utilization, maximum working frequency, and power dissipation are also computed and analyzed for all the described architectures and several experiments are carried out to test the circuits characteristics. The comparison with previously proposed works shows that circuits performance overcome the state-of-the-art architectures, highlighting the effectiveness of the proposed solutions.


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